|Main objectives of the assessment: To enhance understanding of VHDL-based system design, testing, and implementation.To enhance understanding of state machines.To introduce the need for debouncing in practical system implementations.To enhance student competence is presenting complex technical material.
|Brief Description of the assessment: The main task in the group project is to implement a sequence detector using the NEXYS FPGA board, which will be used for the prototyping and testing of the implemented system. Design will take place from scratch, i.e., VHDL code will have to be written, synthesized, debugged, analysed and subsequently used for the programming of the FPGA board. Debouncing strategies will have to be considered as well as power consumption issues. The students are required to: Use Xilinx Vivado in order to design their system, implement a clock divider in their system and show graphs with the signals that are used by their system. Produce a bit file and verify the operation of their system using simulation Present an analysis of the state machine that they propose for their system and explain its suitability for the task in hand. Consider debouncing strategies for dealing with bouncing issues and propose a suitable strategy. Show that they can use Vivado in order to estimate power consumption.
|Learning outcomes for the assessment: After completing this practical work students should be able to: Design systems using VHDL using a suitable design interface. Implement systems on FPGA Design state machines Understand the effect of bouncing and implement effective debouncing strategies. Estimate power consumption of a design.
|Assessment and marking criteria Project report (50%) The project report should be properly presented and should include suitable interpretations and conclusions. Project report will assess: Understanding of the competing design choices in embedded system designCompetence in deploying VHDL for the description of hardware/circuitsKnowledge and understanding of how to compute consumed powerApplication of relevant laboratory skills to embedded system design
Project presentation (30%) The presentation should have proper technical content, structure and coherence, and should be delivered within the allotted time. Project presentation will assess: Understanding of the competing design choices in embedded system designCompetence in deploying VHDL for the description of hardware/circuitsKnowledge and understanding of how to compute consumed power Project demo (20%) Project demo will assess: Competence in deploying VHDL for the description of hardware/circuits. Assessed by checking the functionality of the final system (simulation)Application of relevant laboratory skills to embedded system design
|Assessment method by which a student can demonstrate learning outcomes: Submit a laboratory report that clearly reports the lab work undertaken towards the exercises set out in the assignment brief and providing conclusions and interpretations on the work done. Present work undertaken orally and answer relevant questions following the presentation. Demonstrate the operation of the developed system and answer relevant questions following the demonstration
|Format for the assessment/coursework (Guidelines on the expected format and length of submission): Students are required to: technical report (50%) between 15 and 20 pages, answering the questions in the assignment brief.Presentation (30 %)Demo (20%) demonstrating different components of the hardware implementation.
|Distribution date to students: 09/12/2022
|Submission Deadline: 06/01/2023
|Indicative Reading List: All the information should need is contained in the assignment brief.
|Further information: Not applicable.
Title: Design and implementation of sequence detector on FPGA. Submission deadline: Friday 06 January 2023
Sequence detectors are very important in a variety of applications. The main objective of this group project is to implement a sequence detector for FPGAs. The NEXYS FPGA board will be used for the prototyping and testing of the implemented system (see board schematic on the next page). You are asked to take the steps below for your implementation and presentation:
- Using Vivado, write VHDL code for the implementation of a sequence detector in VHDL using push buttons. Four push buttons should be used for entering symbols (‘1’,’2’,’3’,’4’) and one push button should be used for initialisation.
- Up to 10 symbols could be entered after pressing the initialisation push button. When the sequence “2 3 1 4 3” is entered, then the LEDs should start flashing. Please note that the right sequence of symbols need not necessarily be entered immediately after the initialisation push button is pressed. For example, the sequence “2 4 1 2 3 2 3 1 4 3” should be able to activate the flashing of the LEDs.
- If 10 symbols have been entered but the right sequence of symbols has not appeared yet, then the system should lock and the LEDs should show the following predefined pattern: on, off, on, off, on, off, on, off, on, off, on, off.
- If the system is locked, the user will need to press the initialisation button in order to be allowed to start entering new symbols.
- Synthesise and implement your design (in your report present the RTL and technology schematics).
- Analyse the code (produce summary) and give a brief description of your implementation.
- Use simulation to test your design and display input/output results with a brief description.
- Generate bit-stream.
- Use Vivado to estimate power consumption estimates for your design. Show this estimate in your report.
NOTE: In some cases pushing a push-button will not trigger the expected response in your system. This may be due to the fact that in many cases, pushing a push-button does not create a clean transition from 0 to 1. Instead, the input may bounce back to zero and back to 1 within a very short period of time. In order to deal with this problem, you can try using a low clock frequency. But in general you can debounce the pushbuttons in your design by ensuring that the input is considered to be equal to 1 only after it has remained so for a predefined number of clock cycles.
REQUIRED SOFTWARE TOOL AND SUPPORT FILE
- Vivado® Design Suite from Xilinx.
- General XDC file for NEXYS (provided on Blackboard).
- Joint technical report (50%), with individual assessment of different parts done by group members. The technical report should address all requested tasks and also include conclusions and interpretations. The technical report should be between 15-20 pages and should be submitted to the Taught Programmes Office by the deadline.
2) Presentation (30%)
- Demo (20%) demonstrating individually different components of the hardware implementation.
REPORT AND PRESENTATION STRUCTURE
The technical report consists of the following components:
- Introduction: A presentation of the design considerations (based on system specifications) and an overview of the algorithm to be used.
- Theoretical background: Describing the theoretical model underlying the approach to be used.
- Architecture or Pseudo codes: Describing the architecture (circuit) developed, the arithmetic techniques used…etc. Please note that only short excerpts of VHDL code could be included.
- Implementation approach: Describing the design flow and the implementation approach of different components. Explain difficulties that you may have encountered and the way you overcame these.
- Simulation and implementation results and analysis. Power consumption estimation.
The report should be between 15 and 20 pages (excluding cover page, contents, code listings, appendices) typed using times new roman 12-point font. The oral presentation of the project work should follow the same structure as the technical report.
APPENDIX: DIGILENT NEXYS Video Artix-7 FPGA board
The Nexys Video FPGA Board features a large, high-capacity Artix-7 FPGA device, generous external memories, high-speed digital video ports and a 24-bit audio codec. It is perfectly suited for audio and video processing applications. Compatible with ISE® toolset and the Vivado® Design Suite. It is also supported under the free WebPACK™ license.
Xilinx Artix-7 FPGA (XC7A200T-1SBG484C) Features
- 215360 logic cells in 33650 slices (each slice contains 4 x 6-input LUTs and 8 x flip-flops)
- 13Mbit Fast Block RAM
- 10 x Clock Management Tiles, each with a phase-locked loop (PLL)
- 740 x DSP slices
- Internal clock speeds exceeding 450MHz
- On-chip Analogue-to-Digital Converter (XADC)
- Up to 3.75Gbps GTP transceivers
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