INTRODUCTION
1.1 Aims
(i) To gain familiarity with the rapid prototyping systems available to digital designers today using Field Programmable Gate Arrays (FPGAs).
(ii)To gain an in depth knowledge of the internal details of a simple microprocessor at the logic gate level.
1.2 Objectives
(i) To design and simulate a four bit microprocessor for a specific instruction set. The Xilinx Electronic Design Automation (EDA) tools will allow you to enter your design symbolically as logic gates and then simulate its behaviour to verify that it will operate as you expected.
(ii)To implement the design on a Xilinx FPGA and test it using the DIGILENT demonstration board supplied and examine its performance.
ASSESSMENT IS BY INDIVIDUAL WRITTEN REPORT AND PRESENTATION.
As in other projects, your performance in the laboratory (including attendance) will be taken into account.
A library guide can be found at:
http://www.xilinx.com/itp/xilinx10/books/docs/spartan3e_scm/spartan3e_scm.pdf
THE PROJECT
You are one of a team of freelance consultants that specialise in ASIC design. Your company, Homer’s Advanced RISC Machines (HARM) have been approached to tender for a contract to design a new microprocessor chip intended primarily for video applications.
The customer requires a full custom design and expects to fund a team of twenty people for one year. To convince them that your team can achieve this target you have decided to provide them with a reduced specification processor. Two people will design this processor over a period of six weeks. To achieve this target you have decided to implement the processor on a Field Programmable Gate Array (FPGA) and demonstrate it, with performance
details, in the seventh week.
The EDA package chosen is produced by Xilinx and is called ISE. This allows you to enter your design symbolically (schematic capture) and to simulate, to verify design correctness, before going any further. Full timing simulations will provide you with information that will let you decide how fast your design will operate.
SPECIFICATION
The architectural details of the processor are left to you but for the required application you have been asked to provide a solution that uses minimum area. It does not matter how long the processor takes to run a program, but the number of gates used should be a minimum.
The processor must be able to implement the instructions detailed in Appendix A.
The processor must be able to run the test program given in Appendix B.
You must demonstrate a program of your own choice running on the processor.
DESIGN METHODOLOGY
4.1 Top-Down Design
Top-down design is the process of splitting the system specification (the problem) into conceptually simpler sub-problems. Some of the benefits of top-down design are: improved control of the design process, reduced design time by designing in parallel, reduced effort by eliminating poor solutions sooner.
4.2 Synchronous Design
Your design should contain a single system clock. This should be the only clock that connects to the flip-flops in your design. Sequencing is achieved by using flip-flops with an enable line. Xilinx FPGAs have a low skew clock network predefined.
COMPUTER BASICS
A computer is a general purpose, programmable digital system. It can execute a list of instructions, called a program, to perform a diverse range of tasks. A computer consists of a Central Processing Unit (CPU), memory, input and output. A microprocessor may be used as
the CPU of the computer.
The arrangement of the digital components used to implement the microprocessor is called the computer architecture. This is usually specified by its appearance to a programmer at the lowest level. This description is called its Instruction Set Architecture (ISA). The instructions that you are required to implement are given in Appendix A. The architecture for a simple microprocessor can be split into two parts. The DATAPATH and CONTROL
MICROPROCESSOR DESIGN
A microprocessor executes a collection of instructions (program) that tell the processor what to do. The instruction set defines the data path (ALU, SHIFTER, REGISTERS etc.). The controller tells the data path what to do and when to do it. Defining the controller sets the sequencing rules. With four bits in the operation code up to 16 operations may be specified.
CENTRAL PROCESSING UNIT (CPU)
The CPU consists of registers, an Arithmetic Logic Unit (ALU) and a control unit. The ALU carries out the arithmetic (such as ADD, SUBTRACT) and logic (such as AND, OR) operations. Typically the control unit must interpret and sequence the instructions. This is achieved by reading an instruction, retrieving the required data and performing the desired operation by activating the ALU.
An ALU is a combinational circuit, the design of which is usually split into three parts.
1. Design of the arithmetic unit (built around full adders)
2. Design of the logic unit (using multiplexers)
3. Combination of 1 & 2 using a multiplexer to form the ALU. You are advised to use the library component adsu8 for your arithmetic operations and sr8rled for your shifter. Information on the function of these components can be found in the online Xilinx Library manual. http://www.xilinx.com/itp/xilinx10/books/docs/spartan3_scm/spartan3_scm.pdf
7.1 Instruction Set An instruction manipulates the stored data, and a sequence of instructions constitutes a program. You will need to choose a set of instructions that will be able to carry out the task you have chosen.
7.2 Registers The CPU contains a number of special purpose registers. For example a Program Counter (PC) holds the address of an instruction, Data Registers hold data and the Instruction Register (IR) holds instructions to be decoded by the control logic.
8. Basic Computer Instruction Cycle An instruction cycle consists of fetching an instruction from memory and then executing it. In this simple processor, it will consist of the following steps.
- Fetch the instruction from memory into the instruction register. (T0)
- Decode the instruction. (T1)
- Execute the instruction. (T2)
- Update program counter. (T3)
This process is repeated for each instruction. Timing signals are generated to sequence the events in the fetch/execute cycle. For example, you may choose to have four timing slots (T0,T1,T2,T3) available for each instruction cycle, under control of the system clock. Only one timing signal is active at a given time. A ring counter is useful to implement this.
An op code whose address is in the PC is read from memory into the IR. The PC is then incremented to produce the next address. This can be written in register transfer language as:
T0 : IR <= M[PC]
T3 : PC <= PC + 1
Take for example an instruction to load the B register. Let this instruction have a mnemonic LD B to represent the four bit instruction I3, I2, I1, I0. First, assign a four bit op code to this instruction. Let’s use 1010 in this example. We must generate a control signal, say C1, that will enable the B register in that instruction cycle. Also, let’s have the instruction execution in timing slot T2. The op code must be decoded and combined with T2 to produce the desired control signal C1. This is shown in figure 8.2. 5
You must choose a mnemonic for each of your instructions. Each instruction is then given a unique four bit code. The instruction decoder must use this machine code to generate the required control signals at the required time. A 4-to-16 line decoder is useful for this. Finally, you can write a small assembly language program, convert it (by hand) to machine code, store it in a ROM and run your program!
